( ESNUG 269 Item 7 ) -------------------------------------------- [10/24/97]
Subject: ( ESNUG 267 #10 268 #4 ) Synopsys Vs. Altera Max-Plus II For FPGAs
> I wouldn't buy Altera's VHDL package since you already have Synopsys,
> and it won't give you the vendor independence that Synopsys does.
>
> The Synopsys sales rep. will want you to buy FPGA Compiler which is
> supposed to give better results than Design Compiler for Altera designs.
> Stick with good ole' Design Compiler. The extra expense and hassle of
> FPGA Compiler isn't worth it.
From: Mike Dini <mdini@dinigroup.com>
John -- I have used Synopsys FPGA Express/ Synplicity's Synplify/Exemplar's
Leonardo to do Altera 10k designs. Their Altera interfaces are quite easy.
This engineer is overlooking simulation, though. The Altera simulator is
primitive compared to a verilog/vhdl test bench, and this is where you spend
most of your time. Synthesis is the easy part.
- Mike Dini
The DINI Group
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From: Geoffrey Brown <gbrown@hplms2.hpl.hp.com>
John,
Personally, I'm a big fan of Altera's tools. The synthesis for AHDL is
very fast and error free. While at Cornell, my students and I developed
synthesis tools for a protocol description language that generated AHDL.
This output always compiled flawlessly. In addition, we performed little
or no optimization before generating the AHDL -- the Altera tool did a
really good job of eliminating the chaff. At one point we did the same for
Altera's version of VHDL. Unfortunately, this package was slow and buggy
(3 years ago). My inclination would be to approach the VHDL route with
caution -- test a few simple designs to see if it's bearable.
On the other hand, AHDL is a "trivial" language. With a rigid coding
style, a future port to VHDL might not be such a problem.
- Geoffrey Brown
Hewlett-Packard
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From: [ *I* Didn't Say This ]
Hi, John,
When I used some Altera parts about 3 years ago they didn't even offer VHDL.
AHDL is so similar to VHDL that I simply wrote my code in VHDL then
corrected to AHDL when the compiler complained.
I then wrote out the placed & routed design in VHDL and instantiated
several FPGA designs into a TestBench. We even figured out how to edit
the behavioral VHDL into synthesizable VHDL to feed into Synopsys to
translate to other formats.
And, Max-Plus II does the entire design-flow in one step. In using Altera's
tools, you're doing the right thing.
Because I'm in the Synopsys Inner-Circle program, please keep me anon.
- [ *I* Didn't Say This ]
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