( ESNUG 268 Item 7 ) -------------------------------------------- [10/9/97]
From: "Andrew MacCormack" <andrewm@bristol.st.com>
Subject: DC's Choice Of Flip-flops & Optimization Trashes Design Testablity
Hi, John,
I have a problem with Synopsys's logic optimisation. How do I stop it
generating logic that is slightly faster than the stuff I want but breaks
certain design rules we have. For example, our library has some Flip-Flops
with Q and NotQ outputs and some with just Q. If we are only using Q then
we should always use the cell with only a Q output, otherwise our testability
figures drop to the floor. Synopsys, however, calculates that using the
two-output cell is faster in some conditions and may also optimise out an
inverter so we have the NotQ output used but the Q output hanging. Can I
get it not to do this?
Also, sometimes, it calculates that a reset flip-flop with its reset tied
off is faster than a non-reset flip-flop. This is also a testability no-no,
so can we stop it doing this, too?
At the moment our non-ideal solutions are:
1. In a given design where the (intermittent) problem occurs, set_dont_use
on the problem cells in the library. (This is what we tend to use.)
2. In a given design, solve the second problem by turning off Synopsys's
latest logic optimisation (obviously the design might lose out in other
ways from this.)
3. We could hack the cell library to guarentee these cells are always
slower, but that fraught with problems.
Anyone have any suggestions?
- Andrew R MacCormack
SGS-Thomson Microelectronics
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