( ESNUG 266 Item 6 ) -------------------------------------------- [9/18/97]
From: "J.H.Wu" <dragonwu@faraday.com.tw>
Subject: Characterization Of Combinational Logic for Design-Power
Hi John,
Characterization for Design-Power seems a little bit troublesome for me
since I need to cut each power source (VCC) for each stage in cells. I
hate to do this since I can't find a good way out to cut power for all
the cells in all the libraries I have.
My question is: how do you characterize power for combinational logic
cells for Design-Power (for example, a 2:4 decoder)? Do you group the
last two stages power to establish the output pin look-up table for
Design-power?
- Jeng-huang Wu
Faraday Technology Corp., Taiwan
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