( ESNUG 264 Item 3 ) -------------------------------------------- [9/3/97]
From: Terry_Hussey@3com.com ( Terry Hussey )
Subject: DC -- 1.5 Hours Of "Design Rule Compile" Now Takes Over 24 Hours!
Hi John,
I am experiencing a problem in 97.01 (also in 97.01-01_44683) that I am
hoping someone else might understand (or at least have seen).
I have a design, the top level of which compiled under synopsys3.4b in
roughly 1.5 hours. The top level compile is very simple; I've simplified it
further so that it is just a "link" followed by a "uniquify", followed by a
"compile -only_design_rule". In 3.4b, most of that 1.5 hours is used
fixing design rule violations.
In both 97.01 and 97.01-01_44683, that same compile takes over 24 hours
(basically 24 hours fixing design rule violations). I have tried this
using vendor libraries which were designed for 3.4b and new vendor libraries
designed for 97.01. Again, most of the time (basically 24 hours) is spent
fixing design rules.
I am wondering if anyone has seen this type of thing or can suggest any
experiments. I've tried a number such as always using "best case tree",
turning off automatic wireload selection which chose a chip level wire
load (enclosed mode) and instead chosing a very small wire load.
Thanks,
- Terry Hussey
3Com Switching Division
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