( ESNUG 264 Item 2 ) -------------------------------------------- [9/3/97]
Subject: (ESNUG 262 #4 263 #1) Exactly *WHO* Is Using Behavioral Compiler?
> Dear John,
>
> I do not believe the synopsys advertisements about the performance and
> results of its behavioural compiler.
>
> - David Barda
> CAST laboratory
From: [ Afraid Of My Motorola Bigwigs ]
Hi John,
My name is [ deleted ]. I work at the [ deleted ] division of Motorola.
I heard about the ESNUG posting that dismisses Synopsys Behavioral Compiler
as not being real yet and felt compelled to respond. Our network has a
firewall so I don't have direct access to ESNUG. Would you please post my
response below anonymously. It is very key that my name not be used nor
my division's name used associated with this posting because our bigwigs
have a policy against vendor endorsement.
I understand that Synopsys Behavioral Compiler has recently been dismissed
as not being "real" yet. Based on my experience for the last year working
with Synopsys Behavioral Compiler (BC), I strongly believe that BC is now
sufficiently reliable and efficient to produce low-power, area-efficient
high-volume ASICs. BC did not meet our needs for production ASICs one year
ago, but it does now and we plan to tape out a chip in @ 1 month with the
biggest and most complex block on the chip generated using BC.
I have done an extensive evaluation of BC over the past year, comparing
manual RTL to BC output for 5 blocks that have significant amounts of
datapath, memory, and control. The blocks generated using BC were within
@ 5% of manual RTL in terms of both area and power. But the true strength
of BC is that it enables the designer to spend more time in architectural
exploration and find the best architectural trade-off. Using BC I had
time to develop an architecture that was @ 25% less power than the best
architecture that I had implemented in manual RTL.
BC still requires hardware design expertise to produce very high quality
ASICs (@ 5% of manual RTL), but if the application is less cost-sensitive,
then less hardware design expertise is needed with BC. There is room
for further improvement in BC documentation, error diagnostics, and analysis
information. But from my experience, I found that BC now gives @ 2X
productivity improvement over manual RTL and BC can give area and power
within @ 5% of manual RTL.
- [ Afraid Of My Motorola Bigwigs ]
---- ---- ---- ---- ---- ---- ----
From: [ Texas Instruments, Too! ]
Hi John.
I saw your latest ESNUG mail about BC.
I just wanted to let you know that we just taped out a 270K ATM device
running at 58Mhz that was designed with BC.
Amazingly we had 1st pass layout success, easily achieving the customer's
timing.
Quote from customer: "All Postlayout timing was better than Prelayout
timing".
Please treat this anonymously.
- [ Texas Instruments, Too! ]
---- ---- ---- ---- ---- ---- ----
From: [ I Don't Like Lawyers ]
Hi John:
I've heard a lot of people asking about Behavioral Compiler. Here's my
experience, for the record.
In 1994, I brought in BC with the intention of spending four weeks trying
to apply it directly to my current ASIC design. I worked with an
Application Engineer and spoke quite a bit with Synopsys BC guru's on the
West Coast. After 4 weeks I had produced nothing useful so I abandoned it.
Synopsys was apparently very shocked. They claimed that BC was being used
by all of our competitors. They also blamed the lack of results on the
fact that I did not attend proper training.
I waited 3 years. I was starting a new project and brought BC in again.
It seemed to have matured a bit and the AE's were competent. They
also had an example design similar to my architecture. The deal was
that I would go to a BC training class (which I did). Then I would write
the behavioral code and testbench (which I did). They would "BC" it and
give me back an RTL model and gate netlist which passed the testbench. At
that point I would be obligated to purchase the tool (as long as there were
no surprises). Everyone agreed that this was a perfect target design for BC.
For 6 months they worked on the design. They said over-and-over that they
almost had the RTL working. I finally ended it. Again they were surprised.
I never received a report or explanation for the lack of results.
This is a very honest statement of what happened.
You can draw your own conclusions.
I can only conclude the tool does not work. I am not out to slander
Synopsys - I just felt obligated to share my experience with this tool.
By the way, even if the tool worked ... After writing BC-compliant code
and a testbench, I am not convinced yet that my algorithm is more readable
or compact. We went through many iterations of recoding in order to try
to get BC to correctly handshake with the testbench. The code was difficult
to debug since the entire algorithm was executed in a single cycle. This
forces you to insert lots of debug statements and use source code debug
tools. With RTL it's very easy to see intermediate results between clock
cycles.
Please keep me anonymous.
Thanks.
- [ I Don't Like Lawyers ]
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