( ESNUG 263 Item 10 ) ------------------------------------------- [8/27/97]

From: buehlems@ise.uni-stuttgart.de (Markus Buehler)
Subject: Problems Modeling Tristates With Library Compiler v3.5a

Hello, John:

I'm trying to model a tristate buffer with complementary enable signals 
(e, _e) for the SYNOPSYS library compiler v3.5a.  In the manuals I have
found an example for a D-flip-flop with dual clocks (application notes).
However, I can't apply this solution for my buffer and latches also.
I have tried several possibilities, but they always result in warnings.
Does there exist any solution?

  - Markus Buehler
    University of Stuttgart
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