( ESNUG 263 Item 3 ) -------------------------------------------- [8/27/97]

From: [ A Synopsys DC CAE ]
Subject: Tips In Managing Runtime W/ Design Complier NOT IN DC 1997.01

John, here's a tip that users won't find in the DC 1997.01 release that
they should know about.

At times, designers would like Design Compiler to bypass the area recovery
or downsizing steps.  This can be useful when designers are exploring their
design architecture in the early stages of their design cycle.  With the
interim release of DC 1997.01-44683, Design Compiler has a new variable
which allows the  designer to tradeoff between runtime & quality of results.

This variable is only available in the 1997.01-44683 release.
  
               compile_limit_down_sizing = true/false

Why this variable?  You may be familiar with the log file where you have
seen that the delay cost comes down very rapidly and then at a point, you
only see very small changes in the delay and area cost function.  This is
an indication where Design Compiler is spending some CPU cycles trying to
downsize gates to reduce the load seen by the critical path.  At times, this
may have no major impact in improving the delay.  This variable limits the
down sizing or area recovery step which is causing the extra runtime.  This 
variable should be used as a tradeoff between runtime and quality of
results.  It is ideal for use during the exploration phase.


        Cost | *
    function |  *
             |   *
             |    *
             |     *
             |      *
             |       *                        /Assuming the delta in
             |        ***********            / cost function is very
             |                   ********** /  small at this step.
             |                             **************
             +----------------------------/-------------
                                         /           Runtime
                                        /
                                        By setting this variable,
                                        DC will bypass the area
                                        recovery step thereby reducing
                                        the runtime of your compile runs.


Another variable which can also be considered is:

        compile_use_fast_sequential_mode = true/false

This variable prevents reoptimization of sequential cells off the critical
path.  Typically used as a trade-off between runtime and quality of results.
Ideal for use during the exploration phase.  An example:

  analyze/elaborate
  ....
  ....
  include constraints
  compile_limit_down_sizing = true
  /* Can also consider compile_use_fast_sequential_mode = true */
  compile
  ...
  ....

  /* When ready to do a final run... */
  analyze/elaborate
  ....
  ....
  include constraints
  compile_limit_down_sizing = false
  /* Can also consider compile_use_fast_sequential_mode = false */
  ....
  ....
  compile
  ....
  ...

  - [ A Synopsys DC CAE ]



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