( ESNUG 261 Item 7 ) -------------------------------------------- [5/22/97]

From: "N.Chandrapati" <chandra@synopsys.com>
Subject: HW Design: Creating A Single Cycle Write With Asynchronous Memory

Hi!

We see a problem with doing Asynchronous memory accesses in single-clock
cycle.  The question is : Is it safe to use both clock edges to generate
write enable (gate it with the clock) to the memory.
 
     0      1       2          3
   --       ---------          ----------           
     \_____/         \________/          \_______      Clock

   ------------------           ----------
                     \_________/                        Wr_Enbl

   -------  ---------------------  ----------
   _______X _____VALID___________X __________          ADDR/Data


The problem is at edge 3 where hold time on addr/data will be entirely
dependent on buffers/routing delays.  Another problem is that when we use
both clock-edges, there's a restriction on the duty cycle of the clock.
These problems could be dealt with by trying to meet these by adding delay
lines/buffers - but this is not a reliable solution.

One solution we can think of is to double the memory width so that data from
2 clocks can be written at a time, allowing synchronous write enable.

Any ideas, (other than increasing the memory width), are greatly
appreciated.

  - N. Chandra
    Synopsys