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From: Paul Laberge - PC Tech <plaberge@micron.com>
Subject: Crazy Synopsys Buffering & Time Critical Paths In Synthesis
Hi John,
I've got a time critical vhdl design in which I'm ANDing several values,
but only one is time critical. No matter how I code I just can't get
Synopsys to treat the time critical signal as high priority and
AND it at the last possible place in the tree. I've tried group_path,
using parenthesis, and turning structuring off.
A <= B and C and D and E and TIME_CRIT;
My Synopsys rep says VHDL Compiler ignores parenthesis, so I tried:
TEMP <= B and C and D and E;
A <= TEMP and TIME_CRIT;
But doesn't help at all! Any Ideas?
Also, I have a time critical path that feeds externally from my design,
and several internal loads that are less time critical. Therefore I just
want Synopsys to put a big buffer on the internal copy and drive the
external copy unbuffered. No matter what I do Synopsys seems to want to
drive the output port with the buffered copy, or put no buffer on at all.
Both solutions slow down the output port. Help!
- Paul LaBerge
Micron Electronics
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