( ESNUG 257 Item 1 ) -------------------------------------------- [12/12/96]
From: Byron.Sonner@eagle.ColumbiaSC.NCR.COM (Byron Sonner)
Subject: I Always Use Freshly Squeezed DesignWare Parts For Speed
Dear John,
I just want to share with the ESNUG readers a little script I use to "crunch
down" the DesignWare libraries within Synopsys. We're always interested
in speed first and then area for our compiles. This helps us get there:
foreach(design_name,find(design,{*DW*})) {
current_design design_name
create_clock -period 20 -waveform {0, 10} -name clk
set_clock_skew -ideal -delay 0.0 clk
set_input_delay 19 -clock clk all_inputs()
set_output_delay 1 -clock clk all_outputs()
compile -map_effort high
}
current_design top
set_dont_touch {*DW*}
Experiments on my own designs have shown this improves the speed of designs
with the area not growing significantly.
- Byron Sonner
NCR, Columbia, SC
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