( ESNUG 256 Item 3 ) -------------------------------------------- [11/22/96]
Subject: ( ESNUG 255 #6 ) Can't Constrain "Ideal" PLL Generated Clocks
> I'm trying to create a clock that comes from an internal clock driver.
> I've got no clock tree, just a global clock net, so Synopsys sees
> 10,000 loads on the clock driver. This is a pre-layout netlist, so I
> just want to see an ideal clock. I've tried "set_load 0 CLKNET" but
> this only gets rid of the wire capacitance, there's still 130pf of
> capacitance from clock input pins of all the flops. I've tried:
>
> create_clock_no_input_delay = true
>
> but this doesn't seem to do anything. I've also looked at the
> attribute "propagated_clock", but it's not set. (Isn't this a common
> problem with prelayout netlists that contain PLL's?)
>
> The only thing that works is temporarily disconnecting the clock
> net from it's driver, creating a port, making the clock net to new
> port connection, and then doing a "set_drive 0 new_port". Obviously
> this method is not preferred. Any better ideas?
From: Oren Rubinstein <oren@waterloo.hp.com>
John,
Our standard solution is to instantiate a phony cell called "clock_tree".
You can give it a delay, which sometimes is useful in simulations, and
you can create a Synopsys model for it with a drive strength of 0.
When the chip is routed, this cell is replaced by the real clock tree.
A similar approach would be to put the drive strength of 0 directly in
the PLL model.
- Oren Rubinstein
Hewlett-Packard (Canada) Ltd.
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From: Neil Hastie <hastie@isti.fr>
John,
We hit exactly the same problem with our last design. The solution is
to get your friendly ASIC library supplier to produce a dummy clock
buffer model. (Or do it yourself if you possess a Synopsys Library
Compiler.) This clock buffer model should have zero delay independent
of output load. Use this model until you get a real clock tree.
Hope this helps.....
- Neil Hastie
International Supercomputing Technology Institute
Mulhouse, France
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From: mcur@alcatraz.rtc.sc.ti.com (Mark A. Curry)
Hi John,
What's probably happening is that Synopsys is still calculating a
delay from the wire-load resistance times the 130pf pin capacitance.
Try setting the resistance of that net to zero:
set_resistance 0 CLKNET
- Mark Curry
Texas Instruments ASIC Design Center - San Jose, CA
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From: John_J_Lim_at_3-AP02A@CCGATE.HAC.COM (John Lim)
Hi John
It sounds the like the problem Paul is having is that the clock net is
being buffered up (like crazy) when he tries to compile. I had a
similar case when using an internal clock driver (from a clock
generator). The way I handled it was to put a "set_dont_touch_network
CLKGEN/CLK" where CLKGEN was the clock generator block name and CLK is
the output pin from that block. By setting a dont_touch_network, the
tool will not consider the net for design rule constraints thus
leaving the net unbuffered. Hope this helps.
- John Lim
Hughes Space and Communications
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