( ESNUG 253 Item 11 ) ------------------------------------------- [10/4/96]

From: Atle.Haga@alcatel.no (Atle Haga)
Subject: Yikes!  I Can't Resest "max_capacitance" Post-layout?   Damn!

While receiving a post-layout netlist we usually get some/many design rule
violations depending on the design and the quality of the libraries.
Usually max_capacitance violations can be ignored if they're less than 150%
and you do not want to change the netlist more than necessary.  It seems
Design Compiler is not capable of handling this problem since it will 
try to remove *all* violations.  It is not possible to increase the 
max_capacitance value?!!  (Does anyone not want this? Why?)

We managed by manipulating (subtracting) capacitance from the data in the
annotation-file.  However, this is not our preferred design methodology!
Anyone else having other ways of solving this problem ?

  - Atle Haga
    Alcatel Telecom Norway



 Sign up for the DeepChip newsletter.
Email
 Read what EDA tool users really think.


Feedback About Wiretaps ESNUGs SIGN UP! Downloads Trip Reports Advertise

"Relax. This is a discussion. Anything said here is just one engineer's opinion. Email in your dissenting letter and it'll be published, too."
This Web Site Is Modified Every 2-3 Days
Copyright 1991-2024 John Cooley.  All Rights Reserved.
| Contact John Cooley | Webmaster | Legal | Feedback Form |

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)