( ESNUG 253 Item 10 ) ------------------------------------------- [10/4/96]
From: patrickm@BayNetworks.COM (Patrick Murphy)
Subject: Does Synopsys Synthesis Support VHDL Recursion Now? How?
John,
I recently heard that Synopsys supports Recursion in VHDL, and will
synthesize recursive VHDL code! Recursion is a very powerfull tool, and for
instantiating highly repetitive blocks it would be very useful. I'm sure
the recursive call is closely coupled with the generate statement, and the
generate statement needs a TRUE or FALSE boolean declaration in order to
determine when to stop generating the architectures.
Peter Ashenden of University of Cincinatti has an example of a recursive
call upon a VHDL entity to generate a buffer tree, the paper is called
"Recursive and Repetitive Hardware Models in VHDL". I've read the paper,
and it never states whether the code is synthesizable by Synopsys or not.
If it does support recursion, could you tell me how it does it with perhaps
an example or two? If at all possible I would appreciate a simple example,
something like a clock tree or priority encoder would be nice. It would be
interesting to know if Synopsys can handle Synthesizable Recursive VHDL code
that has synchronous logic in it, thus maybe you can recursively instantiate
several simple state machines.
Also it would be nice to know what the limitations are for Synopsys to
compile this kind of code, I'm sure if you make it too complex the compiler
will probably go out and pick daisies for a few hours before it returns
with a core dump, and one of those wonderful cryptic error messages.
- Patrick J. Murphy
Bay Networks
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