( ESNUG 253 Item 9 ) -------------------------------------------- [10/4/96]
From: landman@hal.com (Howard Landman)
Subject: Dealing With Different Capacitance On Different Pins Of One Bus
Hi, John,
I've got some cells in my library that have different capacitances on
different pins of a bus. The most common case is that all the even-
numbered pins have one capacitance number, and all the odd-numbered ones
have another capacitance.
In the past, we have done a fairly kludgey thing to work around this:
we had our synthesis library have cells with individual pins named (e.g.)
"\A[0]" (all the affected busses were "bit-blasted" into scalar pins).
This is pretty messy, since it means the Verilog out of (and into)
Design Compiler has to not be simulatable due to the Verilog library
cells being bussed. We have to use scripts to "fix" the netlists before
we can do anything else with them. But, it does mean that we can get
the right capacitance (and hence, we hope, accurate timing) on each pin.
On page F-28 of the Library Compiler Reference Manual Vol. 2 version 3.3a
it says that it is legal syntax to have a pin group inside of a bus group:
cell (name) {
bus (name) {
pin (name | name_list) {
... pin description ...
}
}
}
Has anyone else on ESNUG used this feature of Library Compiler successfully?
If so, what is the precise syntax I need? What should the pin names be so
that LC knows they are bits of the bus? Is this order dependent? If so,
which order? (All our busses are MSB first, e.g. bus32 = 31 downto 0 or
[31:0] in Verilog terms.)
Howard A. Landman
HAL Computer Systems, Inc.
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