( ESNUG 253 Item 7 ) -------------------------------------------- [10/4/96]
From: [ Not A Synopsys EDA Developer ]
Subject: Synopsys Patent On Latch Inferencing
John,
Last week's EETimes has a "Late News" article about Synopsys getting a
patent apparently for their latch inferencing rules. I'm curious if
you know more about it than the article states.
It seems to me that awarding such a patent might make it impossible
for any other company to compete with Synopsys based on using a common
subset of Verilog. What do you think?
I considered posting a message to comp.cad.synthesis, but decided against
it because my employer sells synthesis tools, and my questions could
easily be misread or misconstrued.
- [ Not A Synopsys EDA Developer ]
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