( ESNUG 253 Item 1 ) -------------------------------------------- [10/4/96]
Subject: ( ESNUG 251 #8 ) Test Compiler "Moody" W/ Test_Mode and Reset_n
> I have a question about disabling asynchronous resets during test mode.
> Test Compiler requires all asynchronous resets to be disabled during test
> mode. Should this include our primary input "reset_n" ? ... Assume
> active low asynchronous reset for the flip flop and when signal1 = '1'
> then we want to reset the flop. There is no problem when:
>
> (reset_n and (test_mode or not signal1))
>
> There is a problem when:
>
> ((test_mode nand reset_n) nand (reset_n nand signal1))
>
> Even though Test Compiler is infering an asynchonous reset port on
> reset_n. It is not able to realize that reset_n will be a '1' when
> shifting in and out data.
From: zehentner@jh-ger.de (Zehentner Georg)
John,
When there is an asynchronous reset controlled by an internal signal
"signal1" and a primary input "reset_n", it is correct to disable the
control of "signal1" for scan test. This methodology works very well in
my designs.
You have to add a "set_test_hold 1 test_mode", so Test Compiler is sure the
asynchronous reset is only controlled by the primary input "reset_n".
- Georg Zehentner
Heidenhain
---- ---- ---- ---- ---- ---- ---- ---- ----
From: Herve.AUCHROY@st.com (Herve Auch-Roy)
You may try <set_test_hold> command to hold your reset_n input pin to a
desired value (1 in this case) during test compile. Personaly, I would
not mess up the Test Compiler directives with the design itself, as it
appears in the sentence:
(reset_n and (test_mode or not signal1))
To my opinion, *test_mode* refers to silicon implementation, and
*reset_n = 1* refers to test patterns. I would rather do:
[ in my source code ] : (reset_n and not signal1)
[ as Test Compiler directive] : set_test_hold 1 reset_n test_mode
Hope this helps.
- Herve R. Auch-Roy
SGS-Thomson
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