( ESNUG 251 Item 8 ) -------------------------------------------- [9/12/96]
From: Greg Gravunder <gregg@jdc.csg.mot.com>
Subject: Test Compiler Seems "Moody" Concerning Test_Mode and Reset_n
John,
I have a question about disabling asynchronous resets during test mode. Test
Compiler requires all asynchronous resets to be disabled during test mode.
Should this include our primary input "reset_n" ? I have included this
gating and I am still having problems with Test Compiler. The problems
result on only a small amount of the flip-flops and seems to depend on how
Test Compiler generates the logic for this gating. I have always thought
that strobing reset should reset all of the flip flops in the design even if
test_mode (another primary input) is a '1'.
Assume active low asynchronous reset for the flip flop and when signal1 = '1'
then we want to reset the flop. There is no problem when:
(reset_n and (test_mode or not signal1))
There is a problem when:
((test_mode nand reset_n) nand (reset_n nand signal1))
Even though Test Compiler is infering an asynchonous reset port on reset_n.
It is not able to realize that reset_n will be a '1' when shifting in and
out data. I have been told by a Synopsys FAE that test_mode= '1' should not
allow reset_n to reset the flip flop although this has not been sitting well
with me. Any advice on ESNUG would be greatly appreciated.
- Greg Gravunder
Motorola
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