( ESNUG 251 Item 6 ) -------------------------------------------- [9/12/96]
Subject: (ESNUG 249 #3) Design Compiler Puts In Regs w/ D Inputs Tied Low???
>In one of my designs, I have a 32-bit registered output, the top 16 bits of
>which happen to be zero, e.g:
>
> IF clk'EVENT AND clk = '1' THEN
> IF cond THEN
> output <= "0000000000000000" & val_a;
> ELSE
> output <= "0000000000000000" & val_b;
> END IF;
> END IF;
>
>Synopsys seems to insist on synthesising 16 registers with inputs tied to
>ground for the top 16 bits. Is there any way to get Synopsys to blow the
>registers away i.e. have 'output(31 DOWNTO 16)' directly tied to ground?
From: peer@iis.fhg.de (Dieter Peer)
John,
I like hardware description languages, and am happy to see Synopsys behave
like this. Your statements are placed inside the the if...endif. So the
16 zeros can *only* appear after the first (clk'EVENT AND clk =3D '1'), as
you described it. This is the correct result of synthesis and fortunately
remains so after incremental compiles.
On the other hand: What output of your 32-bit-bus would you like to see
*before* the very first clock event?
- Dieter Peer
Fraunhofer-Gesellschaft
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From: Martin Radetzki <radetzki@offis.uni-oldenburg.de>
Dear John,
Registers seem to be holy to logic synthesis - once inferred, they last
forever. I've tried, for example, retiming without success. It should be
possible to write a dc_shell script to detect & remove registers tied to
GND/VDD.
- Martin Radetzki
OFFIS Research Institute
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From: Oren Rubinstein <oren@waterloo.hp.com>
Hello again, John.
I agree DC should get rid of the constant flops, but it doesn't. There are
two cases when it can do it:
1. Logic minimization of *combinational* gates.
2. Eliminating gates whose outputs are unconnected.
Your example doesn't fall into the first category, because the MUX is before
the flops. To achieve what you want, you need to re-arange your code, so
the selector works only on the lower bits. (I assume you didn't do this
because you wanted a more general case; if so, you can have a second
selector after the flops to make some bits "read-only".)
In other words, you want to have a row of flops, followed by a row of
2->1 MUXes which select between the flop and a constant (for each bit)
If the controls are also constant, DC eliminates the MUXes and the flops
that were not selected.
- Oren Rubinstein
Hewlett-Packard (Canada) Ltd.
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From: chang@elvis.ds.boeing.com (Kou-Chuan Chang)
I think that is due to the VHDL code. The signal output get assigned inside
the "clock edge check" and it is 32-bit wide. Also, the signal may be
assigned outside of the "clock edge test" for the asynchronous reset.
if (RSTn = '0') then
output <= (output'range => '0');
elsif (CLK'event and CLK = '1') then
if COND then
output <= "0000000000000000" & val_a;
else
output <= "0000000000000000" & val_b;
end if;
end if;
To have the msb 16-bit without the flipflop, you can try
if ((CLK'event and CLK = '1') then
if COND then
output16 <= val_a;
else
output16 <= val_b;
end if;
end if;
In another concurrent statement
output <= "0000000000000000" & output16;
Hope this helps.
- Kou-Chuan Chang
Boeing
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From: Andy Chomyn <Andy.Chomyn@proteon.com>
John, It's a question of style (as always). Try this outside your process
statement:
output(31 downto 16) <= "0000000000000000" ;
Then your process becomes:
IF clk'EVENT AND clk = '1' THEN
IF cond THEN
output(15 downto 0) <= val_a;
ELSE
output(15 downto 0) <= val_b;
END IF;
END IF;
To be more fancy (or neat) you could alias output(31 downto 16) as
output_upper_word and output(15 downto 0) as output_lower_word.
- Andy Chomyn
Proteon
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