( ESNUG 251 Item 4 ) -------------------------------------------- [9/12/96]
Subject: (ESNUG 250 #6) *Always* Want "Selecting Critical Implementations"
> If I synthesize a 20 bit adder I get around 30ns performance, but if I
> use set_max_delay and compile, the timing is reduced to just over 7ns.
> This option enabled 'Beginning Resource Allocation' to use 'Selecting
> critical implementations', and so a Carry-Look-Ahead adder was picked
> from DW01, instead of a ripple adder.
>
> Why didn't I get the fastest adder from DW01 without set_max_delay?
> And what if the adder is buried around other logic, how do I use
> set_max_delay so that I don't get a ripple adder but Carry-Look_ahead?
> Or is there some secret Synopsys switch known only to the High Priests
> of Synopsys that will always enable 'Selecting critical implementation'?
From: celiac@teleport.com (Celia Clause)
John,
This Verilog example shows how to force a Carry Look Ahead incrementer, but
you can do the same thing for an adder:
always @ (posedge clk or posedge reset)
begin : b1
/* synopsys resource r0:
map_to_module = "DW01_inc",
implementation = "cla",
ops = "inc1";
*/
if (reset) begin
count = 0;
end
else if (enable) begin
count = count + 1; // synopsys label inc1
end
end
Synopsys uses designware to implement counters, adders, comparators, etc.
You can control the type of designware function used by inserting compiler
directives into your code. This example forced a DW01_inc block to be
implemented as a Carry Look Ahead incrementer
- Celia Clause
RadiSys
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