( ESNUG 250 Item 7 ) -------------------------------------------- [9/6/96]
Subject: ( ESNUG 249 #5 ) HELP! I've Got CLI or SWIFT or VSS Memory Leaks!
> I'm encountering a mysterious memory leak in my simulation environment.
> My testbench in VSS uses RTL VHDL, SmartModels, and the CLI C
> interface. I'm running Sun/SunOS4.1.4. There is a memory leak
> somewhere -- the simulator process starts out with a size of ~100
> megs, but after running overnight (about 15ms with a 1ns timebase and
> a 30ns system clock) the process grows to over 600 megabytes!
From: blogs@telxon.com (Brian Logsdon)
Yep! I have seen memory leaks as well, but they have been related to
problems in OpenWindows. I don't ever recall a memory leak problem in VSS,
but if you have WAVES running, that could really suck the memory up.
Check with your sysadmin to see if you have all of the OpenWindows patches
that you need.
- Brian Logsdon
Telxon Corporation
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From: Pier Garino <Pierangelo.Garino@cselt.stet.it>
John,
We experienced the same memory problem in June, when we tried to use the
release V3.4a of VSS. A STAR was issued, but up to now this has not been
solved yet.
We have nearly the same environment as depicted by Ken, i.e. we use a
testbench with RTL synthesizable descriptions + a Smartmodel (rel R40a) of
an SDRAM component (upd4516161).
Until we used the V3.3b VSS version we were able to simulate our testbench
up to more than 500 ms of simulation (28ns clock period - 1ns resolution
got more than 3 days of run time on a Sparcstation 20) without noticing any
problem. The vhdlsim process just took some tens of MBytes.
After the V3.4a announce, we decided to use it to shorten the simulation
times -- faster simulation was one of the improvements claimed by Synopsys.
But when we went to the V3.4a, our simulations just crashed overnight! We
looked into the code, without finding any explanation. The crash appeared on
all the stations and operating systems we tried to use (Sparcstations with
SunOS 4.x, Ultrasparcs with Solaris 2.5, hp700 with HP-UX!) The problem was
always an abnormal increase of the process memory size, which doubles every
time (except for an initial 'offset' value) up to more than 2GBytes, but
still not enough to finish our simulations!!
We then contacted our local Synopsys Support Center (Italy), who asked for a
test case to be analysed. We were able to provide a very compact test case,
where there is just a component instantiated within the testbench (stimuli
supplied directly through a wif file), i.e. the SDRAM SmartModel!
According to them, the problem seems to be located in the swift interface.
The same bug was experienced at the Support Center on the V3.4b, and they
issued a STAR (bug 37573).
The bad part of the story is that we have been told this bug will not be
solved until the next releases are available. This means that for our
design we cannot use the VSS V3.4a (now changed to 3.4b) on any of the
stations we have (including the fast Ultrasparc), so we are still simulating
with the V3.3b, waiting more than 3 days to know the simulation results!!
- Pier Garino
CSELT (Centro Studi E Laboratori Telecomunicazioni)
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