( ESNUG 249 Item 8 ) -------------------------------------------- [8/30/96]
From: dmullen@net.com (David Mullenex)
Subject: Correlating A Mapped Xilinx Design to HDL Advisor 3.4b GTECH
Hi John,
Thanks for running the ESNUG, providing a forum for discussing and sharing
experiences with the $ynop$y$ tool set.
As part of my Xilinx XC4000 FPGA design process, I was using HDL Advisor to
get a pre-mapped prediction of the results my source code would produce. I
used info provided by the HDL Advisor to go back and refine my source code.
Now that I have synthesized my design I would like to take the mapped design
back to HDL Advisor and try correlating the pre-mapped predictions with the
mapped results. Obviously, the Xilinx FPGA architecture and designware make
it hard to correlate back to the Advisor GTECH (Boolean Generic Technology).
I was hoping to use this approach with two objectives. The first to simplify
and somewhat automate the correlation between my mapped design and my source
code. The second, to get a feeling for the relationship between HDL Advisor
GTECH predictions (using only two input logic functions) and the Xilinx FPGA
mapped design.
Has anyone tried this approach successfully? Is this function supported by
HDL Advisor (It's GUI seems to indicate that it can be done.)
- David Mullenex
Network Equipment Technologies
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