( ESNUG 249 Item 1 ) -------------------------------------------- [8/30/96]
Subject: ( ESNUG 247 #3 248 #3) Benchmark & Opinions On Hardware Emulators
From: [ Synopsys Arkos R&D ]
> FYI: Quickturn gate capacity tends to be overstated from our experience;
> "emulation gates" are typically 2-3X smaller than the design gates that
> Design Compiler would tell you about. I think experienced Quickturn users
> understand this distinction, but it does tend to blur comparisons of
> capacity.
From: Don Monroe <Don_Monroe@synnet.com>
> The last sentence of [ Call Me Ishmael ]'s critique of emulation systems
> suggested that emulation is usually 6X faster than simulation. In my
> experience (4 to 5 yrs using Pie/Quickturn) I would say that emulation
> approaches 1 million X of simulation! If he's only getting 6X he's doing
> something wrong.
From: naeem@quickturn.com (Naeem Zafar)
Hi John,
1) Real gates vs. "emulation gates" -- unlike the comment someone made,
emulation gates are NOT 2-3X smaller than the real ASIC gates -- the actual
gate capacity depends on the design style -- much like in an ASIC.
Emulation gate was designed to be a unisex unit of measure which includes a
certain combination of memory bits and logic gates. If one has 64 bit
buses and multi-port RAMs the actual gate capacity of a 250K EMulation gate
capacity Quickturn machine may be only ~130K ASIC gates, but if one has 32
bit buses and mostly single port RAM and mostly flip flops the capacity can
be higher, in some cases closer to 250K actual gates. This issue of
predicting exact capacity is not unique to Quickturn. No vendor in
emulation business can predict exact capacity and one tends to be more
optimistic until one has a few arrows in their back.
2) Like Don Monroe says if someone is getting only 6X speed up with
emulation they are doing something wrong -- Quickturn customers typically
get 100,000 to 1,000,000 times speedup and this speed allows users to
validate software and the chips in the context of the real application.
3) Quickturn can handle designs at RTL level (Verilog and VHDL) in addition
to the gate level.
4) And yes, we do believe in great DAC parties! :^)
- Naeem Zafar
Quickturn
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