( ESNUG 247 Item 6 ) -------------------------------------------- [8/16/96]
Subject: ( ESNUG 246 #6 ) Is DesignWare Worthwhile Or A Waste For Fast DSP?
> I have a team starting a LSI Logic 0.35 micron CMOS, cell based design.
> Chip is fancy two stage FIR filter. First stage is 240 MHz input
> decimator, no multiplies, precomputed lookup and add. ... We have been
> debating the usefulness of DesignWare. Some contend it will
> save time to instantiate pre-optimized Designware functions. Some say we
> are wasting our time because the speed is so high the Designware functions
> are going to require additional optimization and get overhauled like
> everything else. Any recommendations?
From: khelifi@cae.ca (Djoudi Khelifi)
John, DesignWare is useful in this case if:
1- your functions are reused in many designs with the same bit width
2- and/or your functions are so complex (functionality or big width)
3- your functions are pipelined parts
In these cases, the time to (bc_time and schedule your design) will be
reduced and you will get an accurate estimate for area and timing. On
the other hand, the optimization of your precompiled functions requires a
run time which is proportional to your area and timing constraints.
- Djoudi Khelifi
CAE ELECTRONICS Ltd, Canada
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From: ryan@fsd.com (Ken Ryan)
Hi, John, my 2 cents...
I evaluated DesignWare for a fast arithmetic pipeline. It turns out that
while design entry would have been easier using DW parts, my own structures
were faster and smaller (some several times, when I could roll multiple
operations into, say, a single Wallace tree). I daresay you could put in
pipeline registers and get as fast as you need, at the cost of more gates.
What also scared me away was that DesignWare is fairly expensive and is
licensed yearly, which was not a cost-effective solution for me.
- Ken Ryan
Orbital Sciences Corp.
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From: Steve Hwang <steveh@8x8.com>
Hi, John
Recently, I just did some benchmarks on Synopsys Designware. We have
a number of multipliers (17 bits, 33 bits), and the performance of Synopsys
Designware is equal or better than our custom multipliers. We are using
UMC 0.35um standard cell library (in house developed), with the "SS" library
operating condition (TT device model, 125C, 2.7V). With 17 bits "wallace"
type multiplier, we could achieve 10.54ns (Synopsys) for the worst path
delay while our full custom block has a worst path of 11ns (Epic pathmill).
The only catch is the layout area. Full custom is much smaller than the
standard cell layout, but we think if we are using other commercial
datapath layout tool we can further optimize the area and timing of
Synopsys DesignWare.
In our design, it is pad limited design, so the area is not as critical
as other issues (tapeout date).
- Steve Hwang
8x8, Inc.
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From: krag@lsil.com (Kevin R. Grotjohn)
John,
The advantage of DesignWare is that it is generic and can be mapped to
multiple vendors choosing the best architecture and cells based on
area/speed constraints. However if you are doing pipelined DSP you
will need to instantiate the DesignWare parts (DW02_sum, DW02_mac),
since they will not be inferred from the RTL. If you have the LSI TOOLKIT,
invoke lsilbs and choose SuperMacGen; which is an ideal generator for
DSP because it use custom cells in an delay optimized/pipelined sum of
products architecture. Compile time is an order of magnitude faster
than DesignWare, since the technology mapping step does not need to be
done.
I think the unpipelined 16 bit multiply is done in 8ns (lcbg10p), and
you can do even better if you build a pipelined sum of products for
your application. Our multipliers are always faster than Designware,
and we also have a faster parallel adder if you hand place the cells.
- Kevin R. Grotjohn
LSI Logic
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