( ESNUG 247 Item 4 ) -------------------------------------------- [8/16/96]
Subject: (ESNUG 245 #1 246 #4) My Multicycle Path Odyssey With Synopsys...
From: jaf@arl.wustl.edu (Andy Fingerhut)
> process (CLK)
> begin
> if (CLK'event and CLK = '1') then
> if (change_B = '1') then
> B <= A + 1;
> end if;
> end if;
> end process;
From: mr@symbionics.co.uk (Martin Ryder)
>It should be possible to build a 2-to-1 MUX from logic primitives (AND, OR,
>NOT) to give correct behaviour when the two data inputs are the same,
>regardless of whether the select is known. I.E. for data inputs A and B,
>select S, and output Q .......
From: kurt@wsfdb.com (Kurt Baty)
Hi, John,
As Martin suggests, Andy's muxes can be structured as logic primitives to
get around the select "x" problem. The circuit that correctly creates an
enable-able register row has a side benefit that it can be reset to any
value at no extra logic cost per bit. This circuit design is in DesignWare
DW03_reg_s_pl, a register with synchronous set and/or reset and load.
The design employs only two cells per bit. An AOI2N2 or an OAI2N2 and a
D flip-flop are employed per bit, depending on the reset value desired,
a one or a zero. These gates are in most technology libraries, so the
GTECH part should map exactly. This circuit generates a safe
synchronously loadable, synchronously resetable register. It is
guaranteed to come out of reset cleanly, however, do not ungroup
it and do any kind of compile or the retained AND could be optimized away.
If you wish to ungroup it, just don't do a compile afterwards.
This part has been in the library for some number of revs. It's in the
online documentation as well as the DesignWare data book. If you wish to
see the circuit it generates, set the target library to "gtech.db" and
elaborate and compile one.
- Kurt Baty
WSFDB Consulting
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