( ESNUG 247 Item 2 ) -------------------------------------------- [8/16/96]
Subject: (ESNUG 243 #2 246 #2) Synopsys 3.4b Won't Use 8->1 Multiplexers
> Synopsys can not automatically map anything with more than 8 inputs into a
> logic funtion. Therefore an 8:1 mux (which has 8+3=11 inputs) will never
> get chosen! You must actually instantiate it like ...
From: Ross Swanson <swanson@est07.bwi.wec.com>
John, For a 8:1 mux I coded a "case" statement with an integer for the
expression and got a 16:1 built, the 2:1 and the other 8:1 were optimised
out! I'm using v3.4b with the infer_mux attribute.
- Ross Swanson
Northrop-Grumman
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From: krag@lsil.com (Kevin R. Grotjohn)
John, Regarding the infer_mux directive in 3.4a, I tested this new feature
using LSI lcbg10p library using the examples in the Synopsys application
note (DOC-111195). Design Compiler inferred our lcbg10p/mux81h cell just
fine. There are a lot of compiler directives and RTL conventions that
impact how well this works though. In older versions you do have to
directly instantiate it.
Synopsys 3.4a can map to large input function cells, I have tested it for
all logic functions of up to 12 inputs. I assume it can do even higher
input functions -- but congestion problems do become an issue which DC
does not consider.
- Kevin R. Grotjohn
LSI Logic
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> Unfortunately there is no easy way to instantiate multiple components in
> Verilog (in VHDL you can use "generate", but even this is crude.)
> I have built a user designware module called "mux_gen" where you can just
> pass parameters and get one built like you want. (Note: Kurt Baty has
> created a module he calls "mux_any", while mine is similar in function...
From: kurt@wsfdb.com (Kurt Baty)
Hi, John,
The DW01_mux_any is on the Synopsys 3.4b DesignWare CDROM. If you are
running 3.4b and you want to know if the mux_any part is available for you
to use, type the following Unix command:
% ls $SYNOPSYS/dw/dw01/lib/DW01_MUX_ANY*
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY.mra
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY.sim
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY.syn
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY_CFG_SIM.sim
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY_CFG_STR.sim
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY__SIM.sim
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY__SIM.syn
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY__STR.sim
/cadapps/synopsys/synopsys_3.4b/dw/dw01/lib/DW01_MUX_ANY__STR.syn
If you see these files, then the mux_any is available for you to use. It
maps 8:1 muxes. The documentation will, of course, be in the next release.
The part really wasn't supposed to be on the 3.4b CDROM. It was supposed to
be on the 3.5a.
You can use the part as the following Verilog code example shows:
module mux(data_in,mux_sel,data_out);
parameter out_width = 8, sel_width = 5, in_width = 24*8;
input [in_width-1:0] data_in;
input [sel_width-1:0] mux_sel;
output [out_width-1:0] data_out;
wire [out_width-1:0] data_out;
DW01_mux_any #(in_width,sel_width,out_width) mux(data_in,mux_sel,data_out);
endmodule
The only times 8:1 muxes may not be chosen are 1) if your library's 8:1 mux
has an enable pin or 2) the 8:1 speed is less than stacked 2:1 or 4:1s and
you have a high map effort compile.
- Kurt Baty
WSFDB Consulting
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