( ESNUG 247 Item 1 ) -------------------------------------------- [8/16/96]
From: carl@compass-da.com (Carl Newhouse)
Subject: Comparing Two Synopsys/Compass Floorplanning Design Flows
John, in using COMPASS ChipPlanner with Synopsys synthesis for floorplanning
there are two basic approaches:
1) Traditional SDF Low level timing constraints - Timing constraints
that can be passed from Synopsys to ChipPlanner or vice versa via SDF
or a Synopsys constraints file. These Synopsys constraints are
typically in the form of a single constraint per path, or paths which
get constrained via -max_paths -nworst, -cover_design options. The
cover_design in Synopsys generates a constraint for the worst path
through every single input pin of each cell in the design. This
provides essentially complete coverage of the design. There are 2
flows using traditional low level constraints:
a.) Forward Annotation Flow (Synopsys-> ChipPlanner) -- Feed SDF or
Synopsys constraints into the floorplanner to perform timing
driven placement.
b.) Back-Annotation Flow (ChipPlanner->Synopsys) -- Feed SDF and
Synopsys Parasitic Command FIle (containing set_load,
set_resistance, etc.) information for IPO (Inplace Optimization).
PDEF is also generated so Floorplan Manager can take into account
the physical hierarchy during IPO. COMPASS can also generate
selective timing path (SDF out).
2) High level Timing Constraints -- These are constraints independent of
the exact timing path. The constraints apply to a block or the entire
design. Typical high level constraints are: frequency, external delays,
path clusters, multi-cycle constraints etc. The Compass ChipPlanner
Floorplanner (MakeTime Option) can take these Synopsys constraints and
perform placement of the standard cells and eliminate the need to
generate SDF to feed back to the synthesis enviroment. Some specific
examples of Synopsys constraints that can be read into ChipPlanner:
create_clock -name clk -period 20
set_input_delay 3 -clock clk input1
set_output_delay 3 -clock clk output1
report_timing
This approach avoids useless speeding up non-critical paths and lets
the designer use the same Synopsys constraints for synthesis and
floorplaning.
In a nutshell, the two basic flows are:
Using Low Level Constraints Using High Level Constraints
===================== ======================
1 Synthesize Synopsys Synthesize Synopsys
2 Floorplan 1 Floorplan with High level constraints
3 Generate SDF 2 Analyze Timing in Floorplan
4 Load SDF 3 Perform IPO in Floorplan
5 Analyze Timing in Synopsys <Repeat Steps 1-3 if necessary>
6 Synopsys In-Place Optimization
7 Floorplan with ECO changes
<Repeat Steps 3-7 if necessary>
Benchmarking the two basic flows, using a 300K gate cell-based design, I
found the high level approach only took 10 minutes to read into ChipPlanner
(because it was digesting only a 1K constraints file) and 3-4 iterations
were typical. I don't know details for the traditional flow but I suspect
it'll be longer because the traditional SDF low level constraints took ~5
hours just to read into Synopsys (because it's reading a 60MB SDF file.)
I don't have any numbers on how long the entire steps 3-7 would take. It
would be nice to know.
- Carl Newhouse
Compass Design Automation
|
|
