( ESNUG 244 Item 5 ) ---------------------------------------------- [7/25/96]
Subject: (ESNUG 240 #7 242 #6 243 #4) Simulators Giving Frustrating X's
> On the subject of X's in your simulation... About 4 years ago several
> of us discovered this, and it took us a while to convince Synopsys that
> this was a problem with "synthesis and then gate-level simulation
> methodology". Synopsys wrote up a very nice App note that they should be
> handing out to every customer. However, the conclusion was that there is
> nothing wrong with the circuit and it will work perfectly fine, but that
> the problem is with simulation (and as was said before maybe the simulation
> vendors will take note and improve the simulators).
From: Steve Hwang <steveh@8x8.com>
John,
The simulation problem of 'X' propagation is due to the cell definition
of all the MUX cells. If users check their simulation library cell MUX,
it must be built with the simulator primitive ("and", "or", "not" ...).
To avoid the 'X' propagation, users need to define their MUX cell by
using a UDP (User defined primitive table). Here is a Verilog version of
a MUX21:
primitive p_mux21 (q, data1, data0, dselect);
output q;
input data1, data0, dselect;
// FUNCTION : TWO TO ONE MULTIPLEXER
table
//data1 data0 dselect : q
0 0 ? : 0 ;
1 1 ? : 1 ;
0 ? 1 : 0 ;
1 ? 1 : 1 ;
? 0 0 : 0 ;
? 1 0 : 1 ;
endtable
endprimitive
Most simulators support some kind of defined table format, so their users
can define the definition of their own library cells.
- Steve Hwang
8x8 Corp.
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