( ESNUG 244 Item 4 ) ---------------------------------------------- [7/25/96]
Subject: ( ESNUG 242 #4 243 #1) Will Trade My Secret Switches For Yours!
> I look forward to hearing what others find while checking out some of
> those other undocumented commands!
From: Neil Hastie <hastie@isti.fr>
John,
There is nothing very secret about the existance of synopsys switches. All
an inveterate hacker needs to do is pass the dc_shell_exec executable through
the UNIX "strings" command and "grep" for a suitable result. For example,
the following command gives an interesting output listing all compiler
directives hidden or otherwise:
strings -a SYNOPSYS_PATH/dc_shell_exec | grep compile_
...also useful for hunting error messages, etc.
- Neil Hastie
International Supercomputing Technology Institute, France
---- ---- ---- ---- ---- ---- ----
From: Shannon Hill <hill@synnet.com>
John:
Here are all the compile_* strings I found in the design_compiler executable.
Maybe we could start a contest to see who could figure them all out!
(Synopsys employees could contribute, but certainly couldn't claim any
the prizes!)
- Shannon Hill
3COM
P.S. The one I want to know more about is "compile_faster" !!!
compile_assume_fully_decoded_three_state_busses
compile_assume_fully_decoded_tristate_busses
compile_benchmark
compile_characterize_black_boxes
compile_clean_inverters
compile_cost_inverter_removal
compile_cost_vector
compile_create_mux_op_hierarchy
compile_default_critical_range
compile_default_input_transition
compile_disable_area_opt_during_inplace_opt
compile_disable_hierarchical_inverter_opt
compile_dont_touch_annotated_cell_during_inplace_opt
compile_drc_cost_function_vector
compile_enable_master_slave_inference
compile_faster
compile_fix_multiple_port_nets
compile_flags string too long
compile_force_local_dont_care
compile_ignore_area_during_inplace_opt
compile_ignore_footprint_during_inplace_opt
compile_implementation_selection
compile_inplace_changed_list_file_name
compile_instance_name_prefix
compile_instance_name_suffix
compile_iterative_area_seqmap
compile_multiple_port_isolation_logic
compile_mux_mapping
compile_mux_no_boundary_optimization
compile_mux_ungroup_min_data
compile_negative_logic_methodology
compile_no_new_cells_at_top_level
compile_ok_to_buffer_during_inplace_opt
compile_optimization_cost_function_vector
compile_power_analysis_effort
compile_preserve_subdesign_interfaces
compile_preserve_sync_resets
compile_prioritize_design_rule_cost
compile_propagate_unconnects_from_subdesign_inputs
compile_remove_inverter_opt
compile_resyn_duplicate_logic
compile_size_up
compile_smart_multiple_port_fixing
compile_test
compile_test_design_naming_style
compile_update_annotated_delays_during_inplace_opt
compile_use_fast_delay_mode
compile_use_fast_sequential_mode
compile_use_low_timing_effort
compile_verify
fpga_compiler_fpga_only_override
library_compiler_version
lockup_by_test_compiler
optimize_reg_skip_compile
prepare_design_for_compile
report_compile_options
test_compile
test_test_compiler
use_fsm_compiler
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