( ESNUG 243 Item 8 ) ---------------------------------------------- [7/17/96]
From: wyamamo@ibm.net (Wataru Yamamoto)
Subject: VHDL Compiler 3.4b Problems With Generics & Aggregates
Dear John,
VHDL Compiler 3.4b doesn't accept a vhdl description where a sub-block
(template) has a generic specifying width of vector ports like:
entity subblk is
generic(N: integer); -- vector width
port(A: in bit_vector(0 to N-1); -- 'N' specifies the width.
B: out bit);
end subblk;
architecture something of subblk is
begin
B <= A(A'left);
end something;
Plus VHDL Compiler hates it when a formal port is divided by vector indexes
in a port map like:
architecture dc_error of top is
component subblk
generic(N: integer); -- vector width
port(A: in bit_vector(0 to N-1); -- 'N' specifies the width.
B: out bit);
end component;
begin
U0: subblk
generic map(4);
port map(A(0 to 1)=>P0, A(2 to 3)=>P1, -- Error!!!!!!
B =>P2);
end dc_error;
It gives the error:
Error: Cannot determine type of the aggregate
in routine top line 55 in file '...../ex.vhd'
(This error can occur if an aggregate and a generic appear in the
same component instantiation.) (HDL-206)
When will Design Compiler (VHDL Compiler) support the above?
- Wataru Yamamoto
IBM Japan
|
|
