( ESNUG 242 Item 4 ) ---------------------------------------------- [7/11/96]
Subject: ( ESNUG 241 #9 ) Will Trade My Secret Switches For Yours!
> I'd like to see more secret switches "exposed" in ESNUG. In trade, here's
> mine: I was having headaches with Synopsys putting in unnecessary buffers.
> (I figured out that there was no capacitance, fannout, or timing problem, but
> I was still getting two inverters on each output.) Here's the fix:
>
> /* clean up unnecessary inverters */
> compile_clean_inverters = true
>
> (Sure enough. My extra inverters went away. I am wondering why Synopsys
> hasn't published this switch. Could there be some sort of side effect?
> So far, I have had no problems with it.) Has anyone else found any helpful
> undocumented features that they would like to share?
From: [ Jerry's Kids ]
John, keep me anonymous, please. Although the following was found at my
previous job, my current management may not like it. I didn't ask, either.
I remember trying to find as many as possible of these 2 years ago, and I
found out that a few of them were documented in solv-it, as bug workarounds.
I did a search with "hidden variable" or somesuch and got:
ccl_disable (to disable connection_class )
compile_force_local_dont_care (used by compare_design)
force_input_tran_for_output_tran (used by translate)
seqmap_on (enables/disables sequential mapping)
tlud_use_low_timing_effort (used by translate)
use_nonlinear_delay_model (library selection)
I do not know if they are still valid, some may have disappeared, etc.
- [ Jerry's Kids ]
---- ---- ---- ---- ----
From: tims@dct.rti.org ( Tim Sawinska)
John,
My favorite semi-secret switch is "compile_use_low_timing_effort = true".
I've seen it speed up compiles 10X. (And that's with a piece-wise linear
style library.) It makes the neighborhood for timing re-calculation smaller,
and thus faster, for each of those trials you see Synopsys going through.
- Tim Sawinska
Data Communications Technologies
---- ---- ---- ---- ----
From: [ A Little Bird ]
Hi John, Best keep me "anonymous."
Here's a list of variables I extracted from the dc_shell binary source code.
None of these appear in manual pages or in the Synopsys Iview collections.
I don't know what these commands/variables do (that's where the fun is!),
but I'm sure we'd all be grateful to hear from people who figure them out!
Commands:
bc_partition_logic check_clocks
context_check_disable_cmds context_check_enable_cmds
define_function define_rtl_operation
derive_clock_parameters disable_latch_transparency
distribute_capacitance extract_clock_tree
fv_control group_clock_tree
ignore_memory_loop_precedences ignore_memory_precedences
log_to_phys ph_cluster_cell
ph_create_cluster prepare_design_for_compile
report_scc_execution_status reset_iddq_invalid_state
set_iddq_invalid_state set_jtag_bsdl
syntax_check_enable_cmds write_jtag_bsdl
Variables:
annotation_control atpg_bidirect_output_only
channel_width_denominator channel_width_numerator
check_db_checksums combine_vertical_logic_groups
compile_characterize_black_boxes compile_clean_inverters
compile_enable_master_slave_inference compile_resyn_duplicate_logic
compile_use_fast_sequential_mode fast_partitioning
filter_check_real_by_default gen_ignore_bus_bit_order
hdlin_minimize_tree_delay hdlin_reg_test_print
hdlin_report_resource_costs hdlin_resource_sharing_mode
hdlin_share_common_subexpressions hdlin_share_effort
hdlin_tdrs_script_source left_justify_logic_constants
write_new_format_db_files logic_group_height_percent
logic_group_width_percent port_edge_rate
read_flexible_db_files sc_check_file_existence
scc_execute_sh_command scc_print_usage_message
test_force_bidir_pads_inwards test_force_capture_clocks
test_no_three_state_conflicts_after_capture text_unselect_on_button_press
level_sensitive_startpoint_close_active_edge
Perhaps a Synopsys R&D person would like to correct me, but from what I hear,
Synopsys like to include new software pre-release and leave it hidden behind
a switch so that they can test it a while longer. It also gives them a
chance to field test the feature with some luckless soul who can't get by
without it and has to resort to some new feature which perhaps has some
side-effects (such as a new optimisation that can wreck or save your design).
- [ A Little Bird ]
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