( ESNUG 242 Item 2 ) ---------------------------------------------- [7/11/96]
From: gmann@ford.com (Greg Mann)
Subject: The Ford Verilog Coding Style for State Machines
John, I just wanted to share an improved style for encoding state machines
that we've discovered at Ford Microelectronics.
A rather simple modification in the coding style of a state machine can both
shave off area and improve timing. For a particular test case the reported
cell area was 14% less with loose timing. When timing was over-constrained,
the area was 4% less with slightly better timing. The "compare_design"
command was used to verify that the designs were functionally equivalent.
We've seen some variation in the effect of the style change, but in each
case, there was some area improvement.
Our original style was to lump all the combinational logic of the state
machine into a single "always" block and "case" statement like:
always @(state or .....)
// set defaults
...
case (state)
0: begin
...
end
1: begin
...
end
....
endcase
Our modified code simply separates the state decode from the other logic by
putting it into its own separate "always" block. This creates a one-hot
encoding which is used in the original always block.
always @(state)
begin
state0 <= #1 1'b0; // all states default to 0's
state1 <= #1 1'b0;
...
case (state)
0: state0 <= #1 1'b1; // one-hot set to 1
1: state1 <= #1 1'b1;
....
endcase
end
always @(state0 or state1 or ...)
... set defaults here
case (1'b1) // synopsys full_case parallel_case
state0: begin
...
end
state1: begin
...
end
....
endcase
My theory is that area is improved due to better sharing of logic in the
state decode and in the resulting simplification of the logic following the
decode. Anyone else have any clever FSM encoding tricks?
- Greg Mann
Ford Microelectronics Inc.
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