( ESNUG 241 Item 10 ) --------------------------------------------- [6/26/96]
From: krug@avionics.itt.com (Eric Krug)
Subject: Seeking "Gotchas" Using Mixed Mode Cadence With LMC Models
Dear John,
I am currentlydoing a mixed-signal simulation using Cadence Concept, Logic
Work Bench (used in Mixed Signal mode), Leapfrog, and Verilog-XL (all of
which are from release 9502.)
The Synopsys LMC models I'm using include the old-fashioned Verilog
Smartmodels (Release 39) and the generic SWIFTModels (Release 40). We are
in the process of obtaining and installing SWIFTModel Release 40b (this has
Concept symbols for the devices being modeled) and VHDL SWIFTModel Release
8. (I do not intend to use the Verilog models because they will not be
supported after this year.)
What are the gotchas in this approach?
- Eric Krug
ITT Industries
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