( ESNUG 241 Item 8 ) ---------------------------------------------- [6/26/96]
From: kevind@shannon.tellabs.com (Kevin Dewar)
Subject: 'X's Along With Verifying VHDL RTL vs Gates
Dear John,
Our problem is in the handling of 'X's in comparison statements. As we see
it, the use of the built-in comparison operators in VHDL will force the
multi-valued logic through a boolean type "funnel" in a way that the designer
may not have intended and can easily be unaware of.
The effect is that designers can very easily be lured into a false sense of
security by simulating RTL that has been written with IEEE 'std_logic'
multi-value signals and assuming that unknown values will be handled in a
correct manner. They won't, so the gates can simulate differently from the
RTL (but the gates are correct). (A lot of people must think that this
RTL/gates mismatch is a synthesis problem.)
For example, this (Case 1 below) will correctly handle the situation where
check_bit='X' (as long as 'data_valid' has the appropriate value):
if (check_bit /= '1' and data_valid='1') then
fail_reg <= '1';
end if;
Yet this (Case 2 below) will treat a check_bit of 'X' or 'U' as a failure
which will highlight the fact that there is a problem with the logic. This
is found in the RTL simulations:
if (check_bit /= '1') then
fail_reg <= '1';
end if;
And this (Case 3 below) will treat a check_bit of 'X' or 'U' as a pass which
will obscure the fact that there is a problem with the logic. The RTL will
appear to work!
if (check_bit = '0') then
fail_reg <= '1';
end if;
This will synthesise to the same gates as Case 2 (when the problem will be
found -- but be much more difficult and time-consuming to debug).
We probably don't want to have to write the RTL shown below everywhere but
how else can we find this class of bug before synthesis?
if (check_bit = '0') then
fail_reg <= '1';
elsif (check_bit = '1') then
null;
-- synopsys synthesis_off
else
fail_reg <= 'X';
-- synopsys synthesis_on
end if;
We had hoped that we could run all of our verification runs at the RTL level,
and only a handful of functional tests, with timing information to ensure
that the synthesis was OK, at gate level. Now though it looks like we may
need to run all the verification tests at the gate level. Is there a
better way?
- Kevin Dewar & Brendan O'Dowd
Tellabs Ltd., Ireland
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