( ESNUG 241 Item 5 ) ---------------------------------------------- [6/26/96]
From: gmann@ford.com (Greg Mann)
Subject: Looking For A Lazy Way To Deal With Interblock Timing
John,
I'm looking for a method to determine the worst paths in a multi-block design
without reading the entire design into memory and generating timing reports
at that level. (Each block of a rather large design is being compiled
separately and a timing report is generated for it based on the constraints
for the block.) Of course, some of the timing paths will include more than
one block, so the slack numbers reported in each report tell only part of
the story. For such a path, we need a combined slack value to be able
to accurately rank it with other paths in the design. The approach I'm
looking at is the following:
1) Determine the connectivity between modules.
2) Associate reported timing paths from the different
modules based on the connectivity.
3) Combine associated timing paths and report a total
slack value for the total path.
Before I go too far, I was wondering if anyone else had encountered this
problem (or part of it) and had developed a solution. Help!
- Greg Mann
Ford Microelectronics
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