( ESNUG 240 Item 7 ) ---------------------------------------------- [5/9/96]
From: Eric Ryherd <eric@vautomation.com>
Subject: Sheep Dip! -- Synchronous Reset Thru An ALU Still Gives Xes!
Hi John,
I've run across another "FEATURE" of Synopsys that has landed me into a large
heap of Sheep DIP! I have a design that has a number of registers that are
all fed by a simple ALU. Rather than have all of the registers use an
asynchronous reset (at a cost of 1-2 gates per D FF), I simply have the ALU
perform the following operation:
0 "AND" X
And then load the resulting 0 in all of the registers by simply enabling all
of their clock enables. Now, 0 "AND" X normally would produce 0 on any
output of the ALU. After all, 0 "AND" *anything* should be 0, right?
-- well, *not* according to Synopsys! I still get Xes out of my ALU!
Naturally when I try to run my gate-level simulation I never even get out of
reset!
From reading various SOLVIT, app notes and online docs, I see where I could
add the attribute sync_set_reset if there were some registers to attach it
to. But since the block in question is purely combinitorial, what can I do?
(BTW: The code is in VHDL and I'm using V3.4a and targeting the CCL .6 um
CMOS library.)
- Eric Ryherd
VAutomation Inc.
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