( ESNUG 239 Item 7 ) ---------------------------------------------- [4/11/96]
Subject: It's Not Wise To Synthesize ROMs Using Design Compiler
> From: rray@msai.com (Russell Ray)
>
> Has anyone synthesized a ROM and had good success at getting as small a
> design as possible? If so, how did you do it?
>
> - Russell Ray
> Mitsubishi Semiconductor
From: jgais@wd.estec.esa.nl (Jiri Gaisler)
I used synopsys 3.2b to synthesize a 18 kbit ROM (900 x 22 bits). I first
tried synthesizing from VHDL, using a "case" statement with 900 entries.
This failed (of course?) due to insufficient swap space during synthesis
even though I had 300 MB swap available. I then generated a PLA file
instead, which was read in without problems. The initial gate count was
about 5,500 gates. Optimising with flattening and logical structuring took
it down to 3,300 gates, which I though was OK.
The main problem was place and route: the target device was a sea-of-gates
gate array with two metal layers. The vendor's place-and-route tool could
not handle a synthesized ROM very well. (I understod from the vendor that
the gate utilisation in the ROM block was below 20% !) Fortunately, our
vendor could insert hard macros into his base array, so we used a custom
ROM macro in the end.
I guess that the moral of the story is that you should check with your
silicon vendor whether they have experience from synthesized ROMs before
starting a design. The large connectivity of synthesized ROMs seems to be
a problem for some routing tools. Many vendors can provide composite arrays,
with macros for RAM and ROM, which can solve the problem. However, be aware
of that this could increase the NRE cost since a new base array might have
to be developed.
- Jiri Gaisler
European Space Research and Technology Centre
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From: simon@lsil.com (Simon Favre)
You should not be trying to synthesize ROM or RAM from RTL. Small register
files, maybe, but for anything beyond a few hundred gates, you may be MUCH
better off with a memory generated by your Silicon vendor. Many provide
memory compilers that generate the specific configuration you want from a
set of architechtural choices.
You should also be able to get a Synopsys model of the memory that will
allow optimization of the logic around the memory. Many will do this
for either gate-array, or standard-cell. Your NRE doesn't have to go up
if you are doing a gate-array, and you can get by with a small memory
generated from gate-array transistors. If you need the extra density of
a standard-cell memory squeezed into a gate-array, this usually adds cost.
The main problem with synthesized memory blocks is in P&R. This could make
the timing of the memory a nightmare. You could also end up inflating your
die size with all those random gates, when a compiled structure will fit
nicely. It never hurts to ask what's available.
- Simon Favre
LSI Logic Corp.
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