( ESNUG 239 Item 2 ) ---------------------------------------------- [4/11/96]
Subject: (ESNUG 238 #1) The Change_names v3.3b Command Is A Real Dog!
> John, when we run the change_names command in Synopsys on our whole chip
> (somewhere in the neighborhood of 60K - 100K gates), it goes *very* slowly.
> ... When I say very slowly, I mean that it renames 1 net every 3 or 4
> seconds! The command takes roughly 24 hours to complete. ... The best
> workaround for this is to create a Perl script to do the job on your
> Verilog netlists.
From: stereshk@marsha.sanders.lockheed.com (Stephen P. Tereshko)
John, we had similar problems running change_names... the remedy was to throw
the secret switch:
change_names_update_inst_tree = false
Change_names will no longer try to update instance specific attributes
and thus run much much faster.
- Steve Tereshko
Lockheed Sanders
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From: "Jon Saari" <jons@psdc.sps.mot.com>
Hi John,
If the design has many layers of hierarchy it may be beneficial to process
the change_names commands using a "foreach" loop. Change_names report files
with the -verbose option can get very large. Try turning off the "-verbose"
switch.
- Jonathan K. Saari
Motorola
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From: larky@brooktree.com (Steven Larky)
John, we use change names and I've occasionally seen it really slow down
(couple of hours, never a day!). The problem was that a few lower level
modules were looking for a library that we no longer used (old version)
although all the cells existed in the new library. My workaround was to
reset all the designs so they didn't have the old library pointers in them
(design reuse issue).
If that's not it, a second suggestion is to run the change_names command on
the sub-modules first. It runs a _lot_ faster. And then, with just a few
changes at the full chip level, the full chip change_names command goes
quickly as well. This works for us (>100K gates).
Oh, I don't use -verbose (I doubt that is the problem though).
- Steven Larky
Brooktree Corporation
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From: soroc@hail.mpd.tandem.com (Scott Smith)
John;
We too, at Tandem, have run into this problem of *very* slow processing with
the change_names command. We have seen this problem with all versions of
Synopsys since version 3.0c. Our workaround is:
1. Save the design as either verilog or VHDL from the design compiler.
2. Remove all designs from the design compiler (remove_design -all).
Or exit the design compiler and re-start it.
3. Read the newly written code (verilog or VHDL), not
the .db file, back into Synopsys.
4. Issue the change_names command.
It seems as though the .db file contains some attributes about the design
that are confusing the change_names command, thus the slow processing times.
By reading in the gate level netlist (verilog or VHDL) these design
attributes in the database are removed and the change_names command processes
the netlist fairly quickly.
- Scott Smith
Tandem Computers Inc.
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