( ESNUG 239 Item 1 ) ---------------------------------------------- [4/11/96]
From: dblack@apple.com (David C. Black)
Subject: Verilint Saved My Tail With Synthesis & Cadence Verilog Simulation
Hey John,
Here's some actual Verilint output that has saved my tail. Note that neither
the readers in Cadence Verilog nor Synopsys synthesis caught these errors.
`define BLOCK 8'd256
module Example(
Control_i,
Field_i,
Addr_o,
Clk
);
input [7:0] Control_i;
input Field_i;
output [15:0] Addr_o;
input Clk;
reg [15:0] Addr_o;
always @(posedge Clk) begin :ALWAYS_BLK
// Advance by 0, 1 or 2 blocks
Addr_o <= Addr_o + (Control_i[5] && Field_i)
? (`BLOCK << 1)
: ((Control_i[5] || Field_i)
? `BLOCK
: 16'd0);
end//ALWAY_BLK
endmodule//Example
Imagine this code embedded in a large real life design. How long would it
take you to find the errors? What if you use `define for more complex
operations? Do you always remember operator precedences? Here's what
Verilint caught for me:
interHDL inc. Verilint (R) Version 3.12a (C) 1993-1996 interHDL inc.
Linked on Tue Mar 19 15:06:27 PST 1996
Processing source file d.v
(W530) d.v, line 20: A flipflop is inferred: Addr_o
(W19) d.v, line 21: Truncation of extra bits: 8'd256
(W19) d.v, line 23: Truncation of extra bits: 8'd256
(W446) d.v, line 20: * Reading from an output port: Addr_o
(W224) d.v, line 20: Multi-bit expression when one bit expression
is expected: Addr_o + (Control_i[5] && Field_i)
(W180) d.v, line 23: Zero extension of extra bits: 8'd256
Top level modules:
Example
End of interHDL inc. Verilint (R) Version 3.12a, 0 errors, 6 warnings
The first obvious though frequently overlooked error is 8'd256 which should
be changed to 9'd256. I sized the number to ensure Synopsys wouldn't treat
it as a 32 bit number and avoid a 32 bit adder. It was natural to think of
8 bits as holding 256 bits...oops!
The second error involves operator precedence of the ternary ?: function.
An extra level of parentheses should have been added. Here is the
corrected assignment:
Addr_o <= Addr_o + ((Control_i[5] && Field_i)
? (`BLOCK << 1)
: ((Control_i[5] || Field_i)
? `BLOCK
: 16'd0));
The other warnings are useful to synthesis.
I have built verilint into my makefile scripts as a go/no-go check for
simulation and synthesis. It runs extremely fast, and saves me hours of
debug. I always try to ensure that I understand every warning, and turn
off only a very few.
- David C. Black
Apple Computer
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