( ESNUG 238 Item 7 ) ---------------------------------------------- [4/4/96]
[ Editor's Note: "A Wanderer" below is *NOT* Gunes from above; I wouldn't
be that stupid nor careless with an anon user's anonimity. - John ]
From: [ Just A Wanderer ]
Subject: One User's Initial Impressions of Four Cycle-based Simulators
John
If you publish any of the following please keep my name (and company name)
out of it! I have recently (late 1995) talked to all the players in the
Cycle Based arena. A brief summary of what I found:
SpeedSim: as fast as they say it is but it only worked at gate level.
Company fast in reponding to customers; Good support for
Multi-processing too. Very fast compile (but its only from gate
level input.) Verilog only.
Cadence: a complete mess in terms of response to our requests. Not as
fast on real examples as they claim. Does do RT level. Compile
very slow. Verilog only (VHDL promised).
Synopsys: VHDL only, so we did not look as the interest was from hard-nosed
Verilog users ( *you* know the type <grin>).
Viewlogic: looked too far in the future for our needs at the time.
VHDL only (if I remember rightly)
The key thing is this Multi-Value DD stuff (i.e. Cadence and SpeedSim -- I
cannot comment on the technology of the other tools). It sucks! It means
you have to compile (effectively synthesize without optimization and
technology mapping) your nice, relativly abstract RTL into gate level
(logical) operations like NAND, NOR etc. Yeeech! Just for the hell of it
I threw a multiply operation at one of these tools & it neary died of shock!
(OK, you would not normally have a multiply in RTL you are about to stuff
into Design Compiler but + - or *anything* else that would get Synopsys's
DesignWare going is truely bad news!)
The right approach is to evaluate the RTL directly in a cycle-based way.
- [ Just A Wanderer ]
P.S. John, this work has led me to look at VHDL<->Verilog translation, too.
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