( ESNUG 238 Item 3 ) ---------------------------------------------- [4/4/96]
From: Andy.Frazer@idt.com (Andrew Frazer)
Subject: Three Ways To Port From Synopsys To Cadence Dracula
John,
How do other users run layout verification (such as Dracula) on a design that
was synthesized with Synopsys? Synopsys writes out Verilog and VHDL
netlists, but it does not write out the CDL (similar to Spice) format which
Cadence's Dracula prefers. I know of three ways around this:
1.) tell Synopsys to create schematics, translate the output to a schematic
tool (such as Viewlogic) through EDIF, then write out the CDL/Spice
netlist from Viewlogic.
2.) use the Verilog netlist reader in Dracula's LOGLVS.
3.) write a home grown NAWK/C/Perl tool to translate the verilog netlist
into CDL/Spice format.
At IDT, we have adopted #1 as our standard, because we've had limited success
with #2 and never bothered to work on #3. I'd like to hear on ESNUG how
other users have solved this problem.
- Andy Frazer
Integrated Device Technology
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