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From: jaf@leia.wustl.edu (Andy Fingerhut)
Subject: The Change_names v3.3b Command Is A Real Dog!
John, when we run the change_names command in Synopsys on our whole chip
(somewhere in the neighborhood of 60K - 100K gates), it goes *very* slowly.
We're running on Sparc-10 machines with 256 MB of RAM, and the ps command
says that the dc_shell process is using almost 100% of the CPU, so it
shouldn't be swapping. When I say very slowly, I mean that it renames 1 net
every 3 or 4 seconds! The command takes roughly 24 hours to complete.
define_name_rules verilog -allowed "a-zA-Z0-9_$" \
-first_restricted "0-9$" -replacement_char "_"
change_names -hierarchy -verbose -rules verilog > change_names.log
The best workaround for this is to avoid using change_names altogether.
Instead, create a Perl script to do the job on your Verilog netlists.
- Andy Fingerhut
Washington University
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