( ESNUG 237 Item 5 ) ---------------------------------------------- [3/29/96]

From: snowbin@ix.netcom.com (Joe Smith)
Subject: How Do You Synthesize A Digital PLL From Verilog Or VHDL?

Hello John,

I would like to know if anyone out there has described (and successfully
synthesized--using Synopsys or others) an RTL model of a digital Phase
Locked Loop (PLL) using purely Verilog or VHDL constructs.  Examples and
suggestions here on ESNUG are appreciated.

  - Joe Smith
    KTE Comms, Inc.
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