( ESNUG 237 Item 1 ) ---------------------------------------------- [3/29/96]
Subject: ( ESNUG 234 #4 ) Synopsys/Leapfrog Library Incompatibly Issues
> We are just starting an ASIC design. Setting up the environment, we found
> out, that our ASIC vendor (TI) uses both the Synopsys IEEE (etc.) libraries
> and Leapfrog's (we are using Cadence Leapfrog for simulation). Simulation
> only modules use the Leapfrog libraries but synthesizable modules use it
> too. But, when it comes to synthesis, Synopsys' libraries have to be used
> instead.... Now, it seems just to be impossible to use the same set of
> libraries both for synthesis and simulation.!....
From: randy@vela.com (Randy Bolling)
John,
You need to compile the Synopsys libraries that are extensions into the IEEE
library. You will most likely require root access to do this (providing
Leapfrog was installed using root access ownership rights.) After compiling
the libraries, you can use the signed and unsigned packages. Creating the
library "synopsys" first and compiling the related packages into that library
is preliminary to compiling the synopsys packages into the IEEE library.
I usually setup creating the library "synopsys" with:
vhdlcom -work synopsys /vhdl/synopsrc/attributes.vhdl
vhdlcom -work ieee /vhdl/synopsrc/std_logic_textio.vhdl
vhdlcom -work ieee /vhdl/synopsrc/std_logic_misc.vhdl
vhdlcom -work synopsys /vhdl/synopsrc/math_complex.vhdl
vhdlcom -work synopsys /vhdl/synopsrc/math_real.vhdl
vhdlcom -work synopsys /vhdl/synopsrc/sdf_header.vhdl
vhdlcom -work synopsys /vhdl/synopsrc/bv_arithmatic.vhdl
vhdlcom -work synopsys /vhdl/synopsrc/distribution.vhdl
vhdlcom -work synopsys /vhdl/synopsrc/gs_types.vhdl
vhdlcom -work ieee /vhdl/synopsrc/std_logic_arith.vhdl
vhdlcom -work ieee /vhdl/synopsrc/std_logic_entit.vhdl
vhdlcom -work ieee /vhdl/synopsrc/std_logic_component.vhdl
vhdlcom -work ieee /vhdl/synopsrc/std_logic_textio.vhdl
vhdlcom -work ieee /vhdl/synopsrc/std_logic_signed.vhdl
vhdlcom -work ieee /vhdl/synopsrc/std_logic_unsigned.vhdl
vhdlcom -work ieee /vhdl/synopsrc/math_comlex.vhdl
vhdlcom -work ieee /vhdl/synopsrc/math_real.vhdl
vhdlcom -work ieee /vhdl/synopsrc/gs_types.vhdl
Where vhdlcom is the compile script to call up the vhdl compiler (or alias).
Check the command line switch -explicit for certian compilers. Explicit
declaractions will allow you to define the new signed and unsigned versions
of std_logic signed/unsigned arithmetic. Where "-work ieee" and "-work
synopsys" are the target libraries for the compilation. Last time I compiled
to Leapfrog, there were no signifigant issues (as with some vhdl compilers.)
All the code compiled directly, but some of the warnings / errors you might
encounter with various compilers :
- "(others=>'0')" clause for variable width constant declaration of a
Right-Hand value for the Left-Hand signal assignment fails in
compilation. Change to a for loop using 'high and 'low to determine
the bus width.
- Warnings about null bus width is cases where the bus is defined to
have no elements. Ignoring these is ok in most cases.
Libraries such as math complex and math real are compiled to both "synopsys"
and "ieee" to make them easy to reach. (It's merely a convenience!)
Every time you decide to re-compile these libraries, expect to out-of-date
all source code that reaches the libraries. (Meaning, entire ASIC's that are
taped out should have their libraries taped out!) It rarely happens, but
when you restore a tape and go searching for a bug in simulation, and can't
simulate without re-compiling, it leaves one with the feeling that "what if"
a change in the libraries affects the simulation.
- Randy Bolling
Vela Research
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