( ESNUG 232 Item 1 ) ---------------------------------------------- [12/15/95]
Subject: (ESNUG 231 #6) Seeking One Generic Embedded Multiport RAM Array
>We are designing ASICs that include embedded multiport RAM arrays, which
>require using vendors' libraries. The problem is that different vendors
>offer different RAM cells... We are trying to find a common base, so as to
>define a common model of the RAM cells that will yield a design compatible
>with all (or most) vendor libraries, present and future (some sort of an
>"industry-standard" RAM cell).
From: Andy Chomyn <Andy.Chomyn@proteon.com>
John,
What this user is trying to do is somewhere between difficult & impossible:
defining "industry-standard" RAM cells. Although I am not, at present,
working on designs with embedded arrays, in the past on some large designs
(300K+) we looked at embedded arrays from various vendors. As you say they
come in various flavours. The general breakdown in terms of port style are:
1 port R/W.
2 port = 1 Read, 1 Write.
2 port = 1 R/W, 1 Read.
3 port = 2 Read, 1 Write.
WE and OE controls tend to be per word - but I'm sure that now I've said
this, there will be a massive response saying bit controlled ! Also, we
found that building our own RAM design could beat some of the vendors
library designs in terms of gate size. I don't know if it is a good idea
to try to define a common base. Probably better to create a generic
with all combinations.
-- Andy Chomyn
Proteon
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