( ESNUG 231 Item 6 ) ---------------------------------------------- [12/8/95]
From: Lev.Tal@ecitele.com (Lev Tal)
Subject: The Bewildering World Of Embedded Multiport RAM Arrays
Hi, John,
We are designing ASICs that include embedded multiport RAM arrays, which
require using vendors' libraries. The problem is that different vendors
offer different RAM cells:
1. Sizes: some vendors (such as LSI Logic) offer RAM compilers, while
others offer standard sizes. Needless to say, there is no standard
for these "standard" sizes.
2. Synchronous / asynchronous: again, no standard. Seems that the
future trend is to support only _synchronous_ RAMs.
3. Number and type of ports: 2-port? 3-port? Are these ports all R/W,
or whether some are read-only or write-only?
4. Controls: WE and OE control inputs - per bit, or per word?
We are trying to find a common base, so as to define a common model of the
RAM cells that will yield a design compatible with all (or most) vendor
libraries, present and future (some sort of an "industry-standard" RAM cell).
The common model seems to be: synchronous, 2-port (one read and one
read/write), one WE and one OE control input per word. Does this model make
sense? Can one define such "industry-standard" RAM cells? What do vendors
plan to support in the future?
- Tal Lev,
ECI Telecom.
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