( ESNUG 231 Item 5 ) ---------------------------------------------- [12/8/95]
Subject: ( ESNUG 228 #1 ) How To Piss Off Salesman By Minimizing DW Useage
>Here's an example way to minimize usage of DesignWare licenses (in this case
>"SynLib-ALU") that may be of interest to ESNUG readers. When compiling for
>the first time, HDL-Compiler may call up a SynLib-ALU license to get the job
>done. Under many circumstances the compiled design is then written out in a
>hierarchical format, with DesignWare components written out as separate
>submodules in the compiled netlist. The problem comes when you want to
>re-optimze the design for timing, or whatever ... the previously compiled
>hierarchical design with DesignWare components is read in, it will
>automatically tie up SynLib-ALU license and potentially cause other
>designers to wait, or pay more money for another license! To get around
>this, simply write out all designs to be re-compiled as *flat* netlists.
>This eliminates the DesignWare component reference in the module names and
>also stops Synopsys from calling up the "SynLib-ALU" license on a re-compile
>of structural code inside these designs.
From: [ A Synopsys DesignWare R&D Engineer ]
Hey John,
The behavior the user describes (DC requiring a SynLib-ALU license upon
subsequent compiles of designs containing DesignWare parts) allows DC to
revisit the implementation choices for each DesignWare part to see if by
changing the implementation a better circuit can be created. We call this
incremental implementation selection (IIS), and it was created by the
DW engineering team as part of our general charter to improve synthesis
Quality Of Results through automated design re-use.
IIS is a nice feature, because it enables architectural decisions to be
re-made as the synthesis of your chip progresses. In most hierarchical
compile approaches there is some form of time budgeting performed (either
by the user or using characterize); as a design progresses the budgets on
individual blocks often change, due to optimizations made within other
blocks. If these budgets change significantly it may warrant revisiting
an earlier implementation decision; normal logic-level optimization cannot
easily compensate for an incorrect implementation choice.
This user's suggested approach will help reduce the demand for DW licenses,
BUT it comes at some potential optimization expense! A flattened DW part
cannot have its implementation re-selected, so you're stuck with the initial
implementation choice (good or bad.) Synopsys users should be warned of
this trade-off should they decide to follow the approach!
- [ A Synopsys DesignWare R&D Engineer ]
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