( ESNUG 231 Item 4 ) ---------------------------------------------- [12/8/95]
From: greg@cqt.com (Greg Bell)
Subject: There's Even A Clever Way To Work Without Library Compiler!
Hi John,
Here's a way you can do a lot of library-like fakeouts without even having a
Library Compiler license. I believe the only thing you can't do is have
cell functionality described in your library. (Hopefully this isn't a
convenient freebie "bug" that I just broadcasted to Synopsys' corporate
offices so that it'll be fixed in the next release. Doh!)
In other words, you can create fake cells with high drive, RAM cells for
timing through black-box RAMs (see SolvIt), etc. To read the library in, do
a read_lib <sourcename>. You'll get an error about not having the Library
Compiler license, but it will then complete with a "Technology library read
successfully" message. Then do a write_lib <libname> -output <libname>.db
to save it out. For reference, here's an example of some library source
that can be compiled:
library(manly_inverter) {
technology (cmos);
default_output_pin_rise_res : 0.1;
default_output_pin_fall_res : 0.1;
date : "Oct 5, 1995";
revision : 0.1;
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1mA";
pulling_resistance_unit : "1kohm";
capacitive_load_unit (1000, ff);
cell (manly_inverter) {
area : 10 /* area of cell */
pin(i) {
direction : input
capacitance : 0.060 /* capacitance of pin */
fanout_load : 0.060 /* fanout load */
}
pin (zn) {
direction : output
max_fanout : 1000
timing() {
intrinsic_rise : 2.000000 /* intrinsic delay of A1 to Z1 */
intrinsic_fall : 2.000000
rise_resistance : 0.000000 /* drive strength of output port */
fall_resistance : 0.000000
related_pin : "i"
timing_sense : negative_unate
}
}
}
}
Because we had gated clocks and Synopsys doesn't treat the clock *network*
as ideal, just the clock port, we had to create a super-high drive buffer
and put it after the clock gate for each sub-module. This is replaced by
a clock tree at the P&R stage.
- Greg Bell
CommQuest Technologies, Inc.
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