( ESNUG 231 Item 2 ) ---------------------------------------------- [12/8/95]
Subject: ( ESNUG 230 #5 ) Is Synopsys Killing Schematics In Design Analyzer?
>I would like to ask Synopsys users on ESNUG to speak out if anyone has used,
>or desired to use, the schematic cross probing feature of Design Analyzer.
>Or maybe would have used it if it was less buggy. Anyone out there???
>
>I ask this because Synopsys is/has been removing support for schematic cross
>probing, and apparently schematic support in general from Design Analyzer.
>I have been told that this is because no one uses schematics in Design
>Analyzer. I was hoping to make use of it for gate level debugging. Now we
>are required to generate schematic plots. Does anyone care that we pay
>maintenance to have a company *remove* useful features?
From: peer@iis.fhg.de (Dieter Peer)
We regularily use the schematic capabilities of Design Analyzer - very
often in order to _understand_ critical paths or weird simulation results.
Due to different sdf delays before and after layout or to understand the
scan chain this grafical aid is extremely helpful. Synopsys should not take
it away.
- Dieter Peer
Fraunhofer-Gesellschaft Institut fuer Integrierte Schaltungen
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From: taimei.dezeeuw@tempe.vlsi.com (Taimei E. DeZeeuw)
John,
What is the use of Design Analyzer without schematics and schematic probing?
The majority of users are scripting everything and using dc_shell to do
development, but when there is a problem that's when Design Analyzer is
useful. I have found these features to be very helpful in debugging designs.
I would hate to see anyone try to go to schematic hardcopy or searching
through a netlist. Isn't this moving drastically backwards in time? I would
hope these features would not go away.
- Taimei E. DeZeeuw
VLSI Technology, Inc.
[ Editor's Note: Taimei & Dieter, I agree with you 100%! I use the schematic
feature constantly in my consulting practice to get a quick look at what's
causing my client's problems synthesis-wise. Design Analyzer is a lot like
the EDA equivalent of an oscilloscope -- it let's me see the raw gates.
Synopsys removing schematic viewing would be just plain stupid! - John ]
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