( ESNUG 231 Item 1 ) ---------------------------------------------- [12/8/95]
From: vito@synopsys.com (Vito Mazzarino)
Subject: Deadline Extended For SNUG '96 Papers
John,
I just wanted to drop you a quick note to tell you that the deadline for
submitting abstracts for next year's SNUG '96 meeting has been extended to
Friday, December 17th. Please tell the ESNUG readers that we could use more
papers on either design verification or using LMC models. Also, there seems
to be some sort of wrong assumption that just because Synopsys currently
only offers a VHDL simulator that SNUG '96 doesn't want Verilog based papers!
(This couldn't be more wrong!!!!!) Users should e-mail abstracts for
proposed papers directly to me at "vito@synopsys.com"
- Vito Mazzarino
Synopsys SNUG'96 Chair
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