( ESNUG 230 Item 6 ) ---------------------------------------------- [11/16/95]
From: Andy.Frazer@idt.com (Andrew Frazer)
Subject: What's The Skinny On interHDL's "Verilint" ? Good Stuff Or Trash?
John,
We are evaluating "Verilint" which is supposed to flag pre-synthesis warnings
in Verilog source code. We are told this tool is supposed to guide the user
to writing better synthesizable code. We are really interested in hearing
any feedback from people who have used this tool. We are not interested in
the workings of the tool itself, but we would like to know if it actually
helps you improve the quality of your code. For example, please don't just
say "we've been using for N years and we like it". Please tell ESNUG what
you like/dislike about it.
- Andy Frazer
Integrated Device Technology
[ Ed. Note: In replying, if you need anonymity, just ask & you got it! -John ]
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